This invention relates to a method of designing a large-scale integrated LSI circuit, and in particular, to circuit design method using a logic synthesis technique.
Generally, as the LSI has been increased in size with a high speed, a circuit design method using the known EDA (electronic design automation) tool has increasingly became important. Such a circuit design method is normally classified into five phases, namely, (1) a system design, (2) a function/logic design, (3) a layout design, (4) a test design, and (5) a macrocell design.
In the function/logic design phase among the above phases, the LSI to be designed is expressed as a resistor or a combination between the resistors. In this event, the known RTL (register transfer level) description which is obtained in the system design phase is expressed by the use of a hardware description language, such as the known VHDL, to obtain a logic circuit net list of a gate level.
In this case, a constraint, a truth table, a logic equation and a state transition description and like are given as inputs in the function/logic design phase. Further, a state code of a state machine is assigned, a flip-flop is assigned and further, a combination logic is generated. Consequently, the logic circuit is generated as the gate level.
In this event, the logic circuit of the gate level which is used in the function/logic phase includes a variety of logic circuits. Under the circumstances, when the logic synthesis is directly carried out for the logic circuit which is described by the use of the VHDL, the constraints are often satisfied.
To this end, the logic is optimized within the range independent of a semiconductor manufacturing technology. Thereby, the number of the logic gates (chip area) and the number of logic stages are suitably adjusted so as to satisfy the constraints which are requested by an user. In such an adjustment, a redundant logic is eliminated, a logic is opened, and a multi-stage is carried out by the use of a nature of Boolean algebra. Finally, a mapping process is performed for the semiconductor manufacturing technology.
Herein, a low power consumption and a small chip are often considered as the constraint in the LSI. Conventionally, it is normal that the constraint, such as the power consumption and the chip area, is manually applied when the number of the logic gates and the number of the logic stages are adjusted. Consequently, the above conventional technique requires enough time to design the circuit.
On the other hand, the logic circuit to be designed includes, for example, a plurality of logic circuits each of which retains a signal value under a predetermined condition and inputs data under the other condition. In this event, this logic circuit is expressed by the use of a specific description, such as the VHDL. The logic circuit is logically synthesized by a combination of a multiplexer, a delay flip-flop and a feedback loop. Herein, the multiplexer operates by receiving an enable signal and a data signal. The flip-flop is connected to the multiplexer and is turned on and off in response to a timing clock. Further, the feedback loop is connected between the delay flip-flop and the multiplexer.
As mentioned before, the delay flip-flop repeats its on and off operations every time the timing clocks are supplied to the logically synthesized combination of the multiplexer, the delay flip-flop and the feedback loop. Generally, electrical power is largely consumed when the delay flip-flop repeats the on and off operations. Consequently, the above logically synthesized logic circuit must be manually adjusted so as to reduce the power consumption of the logic circuit.
It is therefore an object of this invention to provide a circuit design method which is capable of designing a circuit in a short time.
It is another object of this invention to provide a circuit design method which is capable of realizing a lower power consumption.
It is still another object of this invention to provide a circuit design method which is applicable for a logic circuit having a feedback loop.
It is the other object of this invention to provide a circuit design method which is applicable for a logic circuit which retains a signal value under a predetermined condition and inputs a data signal under the other condition.
It is the other object of this invention to provide a circuit design method which is capable of realizing a lower power consumption and a small chip area by preventing a change due to unnecessary timing clocks.
A method of this invention designs a circuit having a flip-flop which performs an on and off operation in response to timing clocks and a feedback loop.
With such a structure, a logic circuit portion which operates in accordance with an enable signal automatically is extracted. Further, the logic circuit portion is formed by the use of gated clock. In this event, the timing clock is gated by the enable signal. Consequently, the number of on and off operations of the flip-flop in response to the timing clock can be largely reduced.
Thus, according to this invention, the logic circuit having a lower power consumption can be obtained with a simple operation by automatically generating the logic circuit which is formed by the use of the gated clock. This also means that the circuit having a small chip area can be structured.